THE FUTURE OF PROCESSOR => CELL ARCHITECHTURE

02Aug07

START-UP MENU
The cell concept was originally conceived by Sony Inc.‘s Kutaragi who thought that the computers could very well be designed as cells in a biological systems. The architecture as it exists today was the work of three companies: Sony, Toshiba and IBM joined in their hands for the sake of PS-3. IBM also brought it’s chip design expertise and in this case used a very aggressive approach by producing a fully custom design – the chip’s circuitry was designed by hand instead of with automated tools, very few other companies use this approach. IBM also has the industry’s leading silicon process which will be used in the manufacturing. Sony and Toshiba bring mass manufacturing capabilities and knowledge.
BRIEF REVIEW
This basically doesn’t really process the thread of instruction but rather it processes the cells of data or rather chunk of processes of similar types. This is sent to different cells and as a result of which the main processor has nothing to do but to instruct other cells to do its task. According to IBM the Cell performs 10x faster than existing CPUs on many applications. This may sound ludicrous but GPUs (Graphical Processors Units or Graphics cards ) already deliver similar or even higher sustained performance in many non-graphical applications [GPU10] . The technology in the Cell is similar to that in GPUs so such high performance is certainly well within the realm of possibilities. The big difference is though that Cell is a lot more general purpose so can be usable for a wider variety of tasks.
Power consumption has been estimated at 60 – 80 Watts at 4 GHz for the prototype but this could change in the production version.
An individual cell is made of a few elements. A few important of them are:->
1. One Power process element(PPE)
2. Eight(8) Synergistic Processor Elements (SPEs)
3. Direct Memory Access Controller (DMAC)
4. Element Memory Access Controller(EIB)

PPE is a conventional 64 bit high clock speed dual threading capable in-order processor which sets up task for the SPE. It will use high bandwidth memory and I/O subsystems. It uses 512 k of cache but don’t underestimate it as the Cell’s PPE cache is more of a temporary holding area, where the PPE parcels the data and sends it off to a Synergistic Processing Element (SPE). Another interesting point about the PPE is that it includes support for the VMX vector instructions, (also known as “AltiVec” or “Velocity Engine” used currently in Mac). VMX can speed up anything from financial calculations to operating system functions though it (or its PC equivalents) don’t appear to be that widely used currently. One company which does use VMX extensively is Apple who use it to accelerate functions in OS X, it would not have been a huge job for Apple to utilize the PPE in the Cell.
But the RISK(reduced instruction set computing),is being used by the PPE ( for those who don’t know ;It is a belief that RISK lessens the hardware requirement and as result makes the C.P.U cheaper though on the other hand it makes the software programming a tedious job).
A 4GHz PowerPC which acts as PPE sounds like a pretty potent processor until we realize that the PPEs are really just used as controllers in the Cell – the real action is in the SPEs.

SPE :-> The real workers of the cell are these SPEs. In a demo Toshiba presented a Cell processor decoding 48 streams of video, of which only 6 of the SPEs were used for data decoding. Another was used for scaling the screen, and the last can be used for other tasks. The SPEs can function in unison, like decoding streams together, or they can be dedicated to completely separate jobs. The SPEs don’t have any cache, but they do have four 64 KB arrays of private memory, or Load Store (LS) units. This gives them a total of 256 KB of private memory. Current processor automate the use of the memory for tasks like data fetch and branch prediction, but this adds complexity and cost to hardware. The SPEs’ memory is not cache, but instead operates as flexible storage for the little processor. In Cell, programs must manage how this memory is used, and this potentially makes these functions far more efficient and specialized for the programs.

DMA channel :-> It allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit. Many hardware systems use DMA including disk drive controllers, graphics cards, network cards, and sound cards. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without a DMA channel.

EIB :-> The EIB carries data traveling from the PPE and L2 cache to the SPEs and back again. It also connects this data to the Memory Interface Controller (MIC) and the FexIO Front Side Bus (FlexIO FSB). Through the MIC and FlexIO FSB, the EIB moves data from all those inner processors to parts of the computer outside the CPU, including system memory.

The key to the high speed is that there has been no slower part left on the processor from data processing to the critical data movement unlike earlier processor where the slower part was always hided to the consumer. But the best part of this whole new technology has still been not mentioned. Its biggest advantage would be that it will be able to use the other cell’s power installed in other parts of our house to improve our computing performance like using home theatre system’s to boost the frame rate while playing some latest game.

But the problem with all these would be the same as those as that of the multi-core processors; that the programs if not written to reap its power would just make it an average performance improvement. As the programs which could really utilize this abstract architecture would not be cake walk for programmers to code.

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